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SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
20.3
Serial Fast Flash Programming
The Serial Fast Flash programming interface is based on IEEE Std. 1149.1 “Standard Test Access Port and
Boundary-Scan Architecture”. Refer to this standard for an explanation of terms used in this chapter and for a
description of the TAP controller states.
In this mode, data read/written from/to the embedded Flash of the device are transmitted through the JTAG inter-
face of the device.
20.3.1
Device Configuration
In Serial Fast Flash Programming Mode, the device is in a specific test mode. Only a distinct set of pins is signifi-
cant. Other pins must be left unconnected.
Figure 20-7. Serial Programming
TDI
TDO
TMS
TCK
XIN
TST
VDDIO
PGMEN0
PGMEN1
0-50MHz
VDDIO
VDDCORE
VDDIO
VDDPLL
VDDFLASH
GND
VDDIO
GND
PGMEN2
Table 20-20. Signal Description List
Signal Name
Function
Type
Active
Level
Comments
Power
VDDFLASH
Flash Power Supply
Power
VDDIO
I/O Lines Power Supply
Power
VDDCORE
Core Power Supply
Power
VDDPLL
PLL Power Supply
Power
GND
Ground
Clocks
XIN
Main Clock Input.
This input can be tied to GND. In this
case, the device is clocked by the internal
RC oscillator.
Input
32 kHz to 50 MHz